The invention relates to integrated circuit cell architecture and, more particularly, to a system and method for forming templates for input/output (I/O) cells and power cells to improve cell interconnections.
As the speed and the number of I/Os of integrated circuits increases, more designs are migrating to the flip-chip technologies, such as the controlled collapse chip connection (C4) technology. The layout design of power and I/O cells are critical in order to have a floor plan with low power bus drop to each cell, low noise to sensitive analog blocks without compromising the size of the chip, and ease for place and route.
Flip-chip bumps, e.g., C4 bumps, are typically placed at the boundary of the chip. In accordance with conventional design layout techniques, prior art I/O buffer transistors are usually placed a significant distance from the C4 bump IC interface. This distance, and the relatively long wire routes, permit the introduction of parasitics in the interface, and the degradation of the intended signals.
It would be advantageous if a cell template could be designed for I/O cells.
It would be advantageous if the bus connections between I/O cells could be standardized to minimize design and layout time.
It would be advantageous if a standard cell template could be designed to minimize the line trace lengths, and therefore the noise, associated with I/O cell buffer transistors.
Accordingly, a system is provided for forming integrated circuit (IC) interconnections. The system comprises an IC input/output (I/O) surface and a plurality of abutted (interconnected) template cells on the IC I/O surface. Each template cell comprises a first metal layer for busing power, a second metal layer, underlying the first metal layer, for busing power, and a signal routing layer underlying the second metal layer, having a routing channel adjacent to the sides of the cell. In accordance with one aspect of the present invention, an I/O buffer transistor can be grouped with a flip-chip bump and a corresponding contact pad. This grouping simplifies the layout and reduces the physical separation between the I/O buffer transistor and the flip-chip bump.
The first metal layer includes a plurality of parallel bus lines extending from a first side to the rectangular template to an opposite second side. The second metal layer also includes a plurality of parallel bus lines extending from a third side to an opposite fourth side of the template cell. The first and second layer bus lines have connection areas for connection to bus lines in abutting template cells. The routing channel includes a plurality of signal trace lines with connection areas that, likewise, connect to the signal trace lines in abutting template cells.
The cell also includes an I/O connection pad overlying the first metal layer for receiving a solder ball or bump, such as a C4 bump. Each template cell further includes either a via, or a connection trace via combination to connect the pad to either the first or second metal layer bus lines.
For power cells, the flip-chip bumps are connected to a power bus line formed in one of the metal layers. For I/O signal cells, the flip-chip bumps are connected to I/O buffer transistors.
Additional details of the above-mentioned system and a method for forming an IC I/O cell template are discussed in greater detail below.